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features ? 16 channel gps correlator ? 8192 search bins with gps acquisition accelerator ? accuracy: 2.5m cep (stand-alone, s/a off) ? time to first fix: 34s (cold start) ? acquisition sensitivity: ?140 dbm ? tracking sensitivity: ?150 dbm utilizes the arm7tdmi ? arm ? thumb ? processor core ? high-performance 32-bit risc architecture ? high-density 16-bit instruction set ? embeddedice ? (in-circuit emulator) 128 kbyte internal ram 384 kbyte internal rom position technology provided by u-blox fully programmable external bus interface (ebi) ? maximum external address space of 8 mbytes ? up to 4 chip selects ? software programmable 8-bit/16-bit external data bus 6-channel peripheral data controller (pdc) 8-level priority, individually maska ble, vectored interrupt controller ? 2 external interrupts 32 user-programmable i/o lines 1 usb device port ? universal serial bus (u sb) v2.0 full-speed device ? embedded usb v2.0 full-speed transceiver ? suspend/resume logic ? ping-pong mode for isochronous and bulk endpoints 2 usarts ? 2 dedicated peripheral data cont roller (pdc) channels per usart master/slave spi interface ? 2 dedicated peripheral data controller (pdc) channels ? 8-bit to 16-bit prog rammable data length ? 4 external slave chip selects programmable watchdog timer advanced power management controller (apmc) ? peripherals can be d eactivated individually ? geared master clock to reduce power consumption ? sleep state with disabled master clock ? hibernate state with 32.768 khz master clock real time clock (rtc) 2.3v to 3.6v or 1.8v core supply voltage includes power supervisor 1.8v to 3.3v user-definable i/o voltag e for several gpios with 5v tolerance 4 kbytes battery backup memory 9 mm 9 mm 100-pin bga package (lfbga100) pb-free, rohs-compliant gps baseband processor atr0621 4890c?gps?10/06
2 4890c?gps?10/06 atr0621 1. description the gps baseband processor atr0621 includes a 16-channel gps correlator and is based on the arm7tdmi processor core. this processor has a high-perfo rmance 32-bit risc architecture and very low power consump- tion. in addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-t ime control applications. the atr0621 has two usart and an usb device port. this port is co mpliant with the universa l serial bus (usb) v2.0 full-speed device specification. the atr0621 has a direct connection to off-chip memory, including flash, through the external bus interface (ebi). the atr0621 includes full gps firmware, licensed from u-blox ag, which performs the basic gps operation, including tracking, acquisition, navigation and position data output. for normal pvt (position/velocity/time) applications, there is no need for off-chip flash memory or rom. the firmware supports e.g. the nmea protocol (2.1 and 2.3), a binary protocol for pvt data, configuration and debugging, the rtcm pr otocol for dgps, sbas (waas, egnos and msas) and a-gps (aiding). it is also possible to store the configuration settings in an optional external eeprom. for customer -specific applications, a softwar e development kit is available. the atr0621 is manufactured using the atmel ? high-density cmos technology. by combining the arm7tdmi microcontroller core with on-chip sram, 16-channel gps correlator and a wide range of peripheral functions on a monolithic chip, the atr0621 provides a highly-flexible and cost-effective solution for gps applications.
3 4890c?gps?10/06 atr0621 figure 1-1. block diagram nsleep nshdn xt_in nreset tms tck tdo tdi ntrst dbg_en em_da0 em_da15 em_a1 em_a19 clk23 rf_on p0/nantshort p15/anton p31/rxd1 p18/txd1 p22/rxd2 p21/txd2 p2/boot_mode p3/ncs1 p4/ncs0 p5/nwe/nwr0 p6/noe/nrd p11/em_a21 p10/em_a0/nlb p16/neeprom p8/statusled p28/em_a20 p30/agcout0 p7/nub/nwr1 ldo_en ldo_in ldo_out ldobat_in vbat p1/gpsmode0 p12/gpsmode2 p13/gpsmode3 p17/gpsmode5 p23/gpsmode7 p24/gpsmode8 p26/gpsmode10 p27/gpsmode11 p29/gpsmode12 p19/gpsmode6 p25/naadet0 p14/naadet1 p9/extint0 sighi0 siglo0 vbat18 xt_out p20/timepulse usb_dm usb_dp embedded ice arm7tdmi usart1 usart2 pio2 spi usb asb apb pdc2 b r i d g e rom 384k usb transceiver sram 128k power supply manager watchdog jtag pio2 reset controller interface to off-chip memory (ebi) advanced interrupt controller gps accelerator timer counter gps correlators smd generator advanced power manage- ment controller sram rtc pio2 controller special function
4 4890c?gps?10/06 atr0621 2. architectural overview 2.1 description the atr0621 architecture consists of two main buses, the advanced system bus (asb) and the advanced peripheral bus ( apb). the asb is designed for ma ximum performance. it inter- faces the processor with the on-chip 32-bit memories and the external memories and devices by means of the external bus interface (ebi). the apb is designed for accesses to on-chip periph- erals and is optimized for low power consumption. the amba ? bridge provides an interface between the asb and the apb. an on-chip peripheral data controller (pdc2) transfers data between the on-chip usarts/spi and the on-chip and off-chip memories without processor intervention. most importantly, the pdc2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. it can transfer up to 64k contiguous bytes without reprogramming the starting address. as a result, the performance of the microcontroller is increased and the power consumption reduced. the atr0621 peripherals are designed to be easily programmable with a minimum number of instructions. each peripheral has a 16 kbyte address space allocated in the upper 3 mbyte of the 4 gbyte address space. (except for the interrupt controller, which has 4 kbyte address space.) the peripheral base address is the lowest address of its memory space. the peripheral register set is composed of control, mode, data, status, and interrupt registers. to maximize the efficiency of bit manipulation, fr equently written registers are mapped into three memory locations. the first address is used to se t the individual register bits, the second resets the bits, and the third address reads the value stored in the register. a bit can be set or reset by writing a ?1? to the corresponding position at the appropriate address. writing a ?0? has no effect. individual bits can thus be modified without hav ing to use costly read-modify-write and complex bit-manipulation instructions. all of the external signals of the on-chip peripherals are under the control of the parallel i/o (pio2) controller. the pio2 controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. after reset, the user must carefully program the pio2 controller in order to define which peripheral signals are connected with off-chip logic. the arm7tdmi processor operates in little-endian mode on the atr0621 gps baseband. the processor's internal architecture and the arm ? and thumb ? instruction sets are described in the arm7tdmi datasheet. the arm standard in-circuit emulation debug interface is supported via the jtag/ice port of the atr0621. features of the rom firmware are described in software documentation available from u-blox ag, switzerland.
5 4890c?gps?10/06 atr0621 3. pin configuration 3.1 pinout figure 3-1. pinout lfbga100 (top view) atr0621 1 2 3 4 5 6 7 8 9 10 abcdef ghj k table 3-1. atr0621 pinout pin name lfbga100 pin type pull resistor (reset value) (1) firmware label pio bank a pio bank b clk23 g9 in dbg_en h4 in pd em_a1 a6 out em_a2 a5 out em_a3 a4 out em_a4 a2 out em_a5 a3 out em_a6 b5 out em_a7 b4 out em_a8 b2 out em_a9 d4 out em_a10 c2 out em_a11 d6 out em_a12 d7 out em_a13 c3 out em_a14 c1 out em_a15 d5 out notes: 1. pd = internal pull-down resistor, pu = internal pull-up resistor, oh = switched to output high at reset 2. vbat18 represent the internal power supply of the backup power domain, see section ?power supply? on page 21 3. vddio is the supply voltage for the following gpio pins: p1, p2, p8, p12, p14, p16, p17, p18, p19, p20, p21, p23, p24, p25, p26, p27 and p29, see section ?power supply? on page 21 4. vdd_usb is the supply voltage for the following usb pins: usb_dm and usb_dp, see section ?power supply? on page 21 . for operation of the usb interface, supply of 3.0v to 3.6v is required. 5. this pin is not connected
6 4890c?gps?10/06 atr0621 em_a16 c6 out em_a17 f8 out em_a18 b3 out em_a19 c5 out em_da0 b6 i/o pd em_da1 b10 i/o pd em_da2 c7 i/o pd em_da3 c10 i/o pd em_da4 d10 i/o pd em_da5 e7 i/o pd em_da6 e9 i/o pd em_da7 b7 i/o pd em_da8 b8 i/o pd em_da9 a9 i/o pd em_da10 c8 i/o pd em_da11 b9 i/o pd em_da12 d8 i/o pd em_da13 c9 i/o pd em_da14 d9 i/o pd em_da15 e8 i/o pd gnd a1 in gnd a10 in gnd k1 in gnd k10 in ldobat_in k8 in ldo_en h7 in ldo_in k7 in ldo_out h6 out nreset c4 i/o open drain pu nshdn g7 out nsleep j6 out ntrst k2 in pd p0 k9 i/o pd nantshort p1 g3 i/o configurable (pd) gpsmode0 agcout1 table 3-1. atr0621 pinout (continued) pin name lfbga100 pin type pull resistor (reset value) (1) firmware label pio bank a pio bank b notes: 1. pd = internal pull-down resistor, pu = internal pull-up resistor, oh = switched to output high at reset 2. vbat18 represent the internal power supply of the backup power domain, see section ?power supply? on page 21 3. vddio is the supply voltage for the following gpio pins: p1, p2, p8, p12, p14, p16, p17, p18, p19, p20, p21, p23, p24, p25, p26, p27 and p29, see section ?power supply? on page 21 4. vdd_usb is the supply voltage for the following usb pins: usb_dm and usb_dp, see section ?power supply? on page 21 . for operation of the usb interface, supply of 3.0v to 3.6v is required. 5. this pin is not connected
7 4890c?gps?10/06 atr0621 p2 g4 i/o configurable (pd) boot_mode ?0? p3 h5 i/o oh ncs1 ncs1 ?0? p4 a7 i/o oh ncs0 ncs0 ?0? p5 b1 i/o oh nwe/nwr0 nwe/nwr0 ?0? p6 a8 i/o oh noe/nrd noe/nrd ?0? p7 d2 i/o oh nub/nwr1 nub/nwr1 ?0? p8 g2 i/o configurable (pd) statusled ?0? p9 j8 i/o pu to vbat18 extint0 extint0 p10 e4 i/o oh em_a0/nlb em_a0/nlb ?0? p11 h10 i/o oh em_a21 ncs2 em_a21 p12 f3 i/o configurable (pu) gpsmode2 npcs2 p13 g10 i/o pu to vbat18 gpsmode3 extint1 p14 j5 i/o configurable (pd) naadet1 ?0? p15 k5 i/o pd anton p16 e1 i/o configurable (pu) neeprom sighi1 nwd_ovf p17 j4 i/o configurable (pd) gpsmode5 sck1 sck1 p18 k4 i/o configurable (pu) txd1 txd1 ?0? p19 f1 i/o configurable (p u) gpsmode6 siglo1 ?0? p20 h2 i/o configurable (pd) timepulse sck2 sck2 timepulse p21 f2 i/o configurable (pu) txd2 txd2 ?0? p22 h8 i/o pu to vbat18 rxd2 rxd2 p23 h3 i/o configurable (pu) gpsmode7 sck sck mclk_out p24 h1 i/o configurable (p u) gpsmode8 mosi mosi ?0? p25 d1 i/o configurable (pd) naadet0 miso miso ?0? p26 g8 i/o configurable (pu) gpsmode10 nss npcs0 ?0? p27 e2 i/o configurable (pu) gpsmode11 npcs1 p28 g1 i/o oh em_a20 ncs3 em_a20 p29 e3 i/o configurable (pu) gpsmode12 npcs3 p30 g5 i/o pd agcout0 agcout0 ?0? p31 h9 i/o pu to vbat18 rxd1 rxd1 rf_on k6 out pd sighi0 f9 in siglo0 e10 in tck j3 in pu table 3-1. atr0621 pinout (continued) pin name lfbga100 pin type pull resistor (reset value) (1) firmware label pio bank a pio bank b notes: 1. pd = internal pull-down resistor, pu = internal pull-up resistor, oh = switched to output high at reset 2. vbat18 represent the internal power supply of the backup power domain, see section ?power supply? on page 21 3. vddio is the supply voltage for the following gpio pins: p1, p2, p8, p12, p14, p16, p17, p18, p19, p20, p21, p23, p24, p25, p26, p27 and p29, see section ?power supply? on page 21 4. vdd_usb is the supply voltage for the following usb pins: usb_dm and usb_dp, see section ?power supply? on page 21 . for operation of the usb interface, supply of 3.0v to 3.6v is required. 5. this pin is not connected
8 4890c?gps?10/06 atr0621 tdi j2 in pu tdo k3 out tms j1 in pu usb_dm f10 i/o usb_dp d3 i/o vbat j7 in vbat18 (2) g6 out vdd18 e6 in vdd18 f7 in vdd18 f6 in vddio (3) e5 in vdd_usb (4) f5 in xt_in j9 in xt_out j10 out nc (5) f4 - table 3-1. atr0621 pinout (continued) pin name lfbga100 pin type pull resistor (reset value) (1) firmware label pio bank a pio bank b notes: 1. pd = internal pull-down resistor, pu = internal pull-up resistor, oh = switched to output high at reset 2. vbat18 represent the internal power supply of the backup power domain, see section ?power supply? on page 21 3. vddio is the supply voltage for the following gpio pins: p1, p2, p8, p12, p14, p16, p17, p18, p19, p20, p21, p23, p24, p25, p26, p27 and p29, see section ?power supply? on page 21 4. vdd_usb is the supply voltage for the following usb pins: usb_dm and usb_dp, see section ?power supply? on page 21 . for operation of the usb interface, supply of 3.0v to 3.6v is required. 5. this pin is not connected
9 4890c?gps?10/06 atr0621 3.2 signal description table 3-2. atr0621 signal description module name function type active level comment ebi em_a0 to em_a21 external memory address bus output ? all valid after reset em_da0 to em_da15 external memory data bus i/o ? internal pull-down resistor ncs0 to ncs1 chip select output lo w output high in reset state ncs2 to ncs3 chip select output lo w output high in reset state nwr0 lower byte write signal output low output high in reset state nwr1 upper byte write signal output low output high in reset state nrd read signal output low output high in reset state nwe write enable output low out put high in reset state noe output enable output low out put high in reset state nub upper byte select (16-bit sram) out put low output high in reset state nlb lower byte select (16-bit sram) o utput low output high in reset state boot_mode boot mode input input ? pio-controlled after reset, internal pull-down resistor usart txd1-2 transmit data output output ? pio-controlled after reset rxd1-2 receive data input input ? pio-controlled after reset sck1-2 external synchronous serial clock i/o ? pio-controlled after reset usb usb_dp usb data (d+) i/o ? usb_dm usb data (d-) i/o ? apmc rf_on output ? interface to atr0601 aic extint0-1 external interrupt request input high/ low/ edge pio-controlled after reset agc agcout0-1 automatic gain control output ? interface to atr0601 pio-controlled after reset rtc nsleep sleep output output low interface to atr0601 nshdn shutdown output output low connect to pin ldo_en xt_in oscillator input input ? rtc oscillator xt_out oscillator output output ? rtc oscillator spi sck spi clock i/o ? pio-controlled after reset mosi master out slave in i/o ? pio-controlled after reset miso master in slave out i/o ? pio-controlled after reset nss/npcs0 slave select i/o low pio-controlled after reset npcs1-3 slave select output low pio-controlled after reset wd nwd_ovf watchdog timer overflow output ? pio-controlled after reset pio p0-31 programmable i/o port i/o ? input after reset (except p3 to p7 , p10, p11, p28) note: 1. the usb transceiver is disabled if vdd_usb < 2.0v. in this case the pins usb_dm and usb_dp are connected to gnd (internal pull-down resistors). the usb transceiver is enabled if vdd_usb is within 3.0v and 3.6v.
10 4890c?gps?10/06 atr0621 gps sighi0 digital if input ? interface to atr0601 siglo0 digital if input ? interface to atr0601 sighi1 digital if input ? pio-controlled after reset siglo1 digital if input ? pio-controlled after reset timepulse gps synchronized time pulse output ? pio-controlled after reset config gpsmode0-12 gps mode input ? pio-controlled after reset statusled status led output ? pio-controlled after reset neeprom enable eeprom support input low pio-controlled after reset anton active antenna power on output output ? pio-controlled after reset nantshort active antenna short circuit detection input input low pio-controlled after reset naadet0-1 active antenna detection input input low pio-controlled after reset jtag/ice tms test mode select input ? internal pull-up resistor tdi test data in input ? internal pull-up resistor tdo test data out output ? outp ut high in reset state tck test clock input ? internal pull-up resistor ntrst test reset input input low internal pull-down resistor dbg_en debug enable input high internal pull-down resistor clock clk23 clock input input ? interface to atr0601, schmitt trigger input mclk_out master clock output output ? pio-controlled after reset reset nreset reset input i/o low open drain with internal pull-up resistor power vdd18 power ? core voltage 1.8v vddio power ? variable i/o voltage 1.65v to 3.6v vdd_usb power ? usb voltage 0 to 2.0v or 3.0vto 3.6v (1) gnd power ? ground ldobat ldobat_in power ? 2.3v to 3.6v vbat power ? 1.5v to 3.6v vbat18 out ? 1.8v backup voltage ldo18 ldo_in ldo in power ? 2.3v to 3.6v ldo_out ldo out power ? 1.8v core voltage, maximum 80 ma ldo_en ldo enable input ? table 3-2. atr0621 signal description (continued) module name function type active level comment note: 1. the usb transceiver is disabled if vdd_usb < 2.0v. in this case the pins usb_dm and usb_dp are connected to gnd (internal pull-down resistors). the usb transceiver is enabled if vdd_usb is within 3.0v and 3.6v.
11 4890c?gps?10/06 atr0621 3.3 setting gpsmode0 to gpsmode12 the start-up configuration of a rom-based syst em without external non-volatile memory is defined by the status of the gpsmode pins after system reset. alternatively, the system can be configured through message commands passed through the serial interface after start-up. this configuration of the atr0621 can be stored in an external non-volatile memory like flash memory or eeprom. default designates settings used by ro m firmware if gpsmode configu- ration is disabled (gpsmode0 =0). in the case that gpsmode pins with internal pull-up or pull-down resistors are connected to gnd/vdd18, additional current is drawn over these resistors. especially gpsmode3 can impact the back-up current. 3.3.1 enable gpsmode pin configuration if the gpsmode configuration is enabled (gpsmode0 = 1) and the other gpsmode pins are not connected externally, the reset default values of the internal pull-down and pull-up resistors will be used. table 3-3. gpsmode functions pin function gpsmode0 (p1) enable conf iguration with gpsmode pins gpsmode1 (p9) this pin (extint0) is used for fixnow? functionality and not used for gpsmode configuration gpsmode2 (p12) gps sensitivity settings gpsmode3 (p13) gpsmode4 (p14) this pin (naadet1) is used as active antenna supervisor input and not used for gpsmode configuration. this is the defaul t selection if gpsmode configuration is disabled. gpsmode5 (p17) serial i/o configuration gpsmode6 (p19) gpsmode7 (p23) usb power mode gpsmode8 (p24) general i/o configuration gpsmode9 (p25) this pin (naadet0) is used as active antenna supervisor input and not used for gpsmode configuration gpsmode10 (p26) general i/o configuration gpsmode11 (p27) gpsmode12 (p29) serial i/o configuration table 3-4. enable configuration with gpsmode pins gpsmode0 (reset = pd) description 0 (1) ignore all gpsmode pins. the default settings as indicated below are used. 1 use settings as specified with gpsmode[2, 3, 5 to 8, 10 to 12] note: 1. leave open
12 4890c?gps?10/06 atr0621 3.3.2 sensitivity settings for all gps receivers the sensitivity depends on the integration time of the gps signals. there- fore there is a trade-off between sensitivity and the time to detect the gps signal (time to first fix). the three modes, ?fast acquisition?, ?normal? and ?high sensitivity?, have a fixed integra- tion time. the ?normal? mode, recommended for the most applications, is a trade off between the sensitivity and ttff. the ?fas t acquisition? mode is optimized for fast acquisition, at the cost of a lower sensitivity. the ?high sensitivity? mode is optimized for higher sensitivity, at the cost of longer ttff. the ?auto? mode adjusts the integration time (sensitivity) automatically according to the measured signal levels. that m eans the receiver with this setting has a fast ttff at strong signals, a high sensitivity to acqu ire weak signals but some times at medium sig- nal level a higher ttff as the ?normal? mode. these sensitivity settings af fect only the startup performance not the tracking performance. 3.3.3 serial i/o configuration the atr0621 features a two-stage i/o message and protocol selection procedure for the two available serial ports. at the first stage, a certai n protocol can be enabled or disabled for a given usart port or the usb port. selectable protocols are rtcm, nmea and ubx. at the second stage, messages can be enabled or disabled for each enabled protocol on each port. in all con- figurations discussed below, all protocols are enabled on all ports. but output messages are enabled in a way that ports app ear to communicate at only on e protocol. however, each port will accept any input message in any of the three implemented protocols. table 3-5. gps sensitivity settings gpsmode3 (fixed pu) gpsmode2 (reset = pu) description 0 (1) 0 auto mode 0 (1) 1 (2) fast mode 1 (2) 0 normal mode (default rom value) 1 (2) 1 (2) high sensitivity notes: 1. increased back-up current 2. leave open table 3-6. serial i/o configuration gpsmode12 (reset = pu) gpsmode6 (reset = pu) gpsmode5 (reset = pd) usart1/usb (output protocol/ baud rate (kbaud)) usart2 (output protocol/ baud rate (kbaud)) messages (1) information messages 000 (2) ubx/57.6 nmea/19.2 high user, notice, warning, error 0 0 1 ubx/38.4 nmea/9.6 medium user, notice, warning, error 01 (2) 0 (2) ubx/19.2 nmea/4.8 low user, notice, warning, error 01 (2) 1 ?/auto ?/auto off none 1 (2) 00 (2) nmea/19.2 ubx/57.6 high user, notice, warning, error 1 (2) 0 1 nmea/4.8 ubx/19.2 low user, notice, warning, error 1 (2) 1 (2) 0 (2) nmea/9.6 ubx/38.4 medium user, notice, warning, error 1 (2) 1 (2) 1 ubx/115.2 nmea/19.2 debug all notes: 1. see table 3-7 to table 3-10 on page 13 , the messages are described in the antaris4 protocol specification 2. leave open
13 4890c?gps?10/06 atr0621 both usart ports and the usb port accept input messages in all three supported protocols (nmea, rtcm and ubx) at the configured baud rate. input messages of all three protocols can be arbitrarily mixed. response to a query in put message will always use the same protocol as the query input message. the usb port does only accept nmea and ubx as input protocol by default. rtcm can be enabled via protocol messages on demand. in auto mode, no output message is sent out by default, but all input messages are accepted at any supported baud rate. again, usb is restricted to only nmea and ubx protocols. response to query input commands will be given the same protocol and baud rate as it was used for the query command. using the respective configuration commands, periodic output messages can be enabled. the following message settings are used in the tables below: table 3-7. supported messages at setting low nmea port standard gga, rmc ubx port nav sol, svinfo mon except table 3-8. supported messages at setting medium nmea port standard gga, rmc, gsa, gsv, gll, vtg, zda ubx port nav sol, svinfo, posecef, posllh, status, dop, velecef, velned, timegps, timeutc, clock mon except table 3-9. supported messages at setting high nmea port standard gga, rmc, gsa, gsv, gll, vtg, zda, grs, gst proprietary pubx00, pubx03, pubx04 ubx port nav sol, svinfo, posecef, posllh, status, dop, velecef, velned, timegps, timeutc, clock mon schd, io, ipc, except table 3-10. supported messages at setting debug (additional undocumented message may be part of output data) nmea port standard gga, rmc, gsa, gsv, gll, vtg, zda, grs, gst proprietary pubx00, pubx03, pubx04 ubx port nav sol, svinfo, posecef, posllh, status, dop, velecef, velned, timegps, timeutc, clock mon schd, io, ipc, except rxm raw (raw message support requires an additional license)
14 4890c?gps?10/06 atr0621 the following settings apply if gpsmode configuration is not enabled, that is, gpsmode = 0 ( rom-defaults ): 3.3.4 usb power mode for correct response to the usb host queries, the device has to know its power mode. this is configured via gpsmode7. if set to bus powered , an upper current limit of 100 ma is reported to the usb host; that is, the device classifies itself as a ?low-power bus-powered function? with no more than one usb power unit load. 3.3.5 active antenna supervisor the two pins p0/nantshort and p15/anto n plus one pin of p25/naadet0/miso or p14/naadet1 are always initialized as gener al purpose i/os and used as follows: p15/anton is an output which can be used to switch on and off antenna power supply. input p0/nantshort will indicate an antenna short circuit, i. e. zero dc voltage at the antenna, to the firmware. if the antenna is switched off by output p15/anton, it is assumed that also input p0/nantshort will signal zero dc voltage, i.e. switch to its active low state. input p25/naadet0/miso or p14/naadet1 will i ndicate a dc current in to the antenna. in case of short circuit, both p0 and p25/p14 will be active, i.e. at low level. if the antenna is switched off by output p15/anton, it is assumed that also input p25/naadet0/miso will signal zero dc current, i.e. switch to its active low state. which pin is used as naadet (p14 or p25) depends on the settings of gpsmode11 and gpsmode10 (see table 3-14 on page 15 ). table 3-11. serial i/o default setting if gpsm ode configuration is deselected (gpsmode0 = 0) usb nmea usart1 nmea usart2 ubx baud rate (kbaud) 57.6 57.6 input protocol ubx, nmea ubx, nmea, rtcm ubx, nmea, rtcm output protocol nmea nmea ubx messages gga, rmc, gsa, gsv gga, rmc, gsa, gsv nav: sol, svinfo mon: except information messages (ubx inf or nmea txt) user notice, warning, error user, notice, warning, error user, notice, warning, error table 3-12. usb power modes gpsmode7 (reset = pu) description 0 usb device is bus-powered (maximum current limit 100 ma) 1 (1) usb device is self-powered (default rom value) note: 1. leave open
15 4890c?gps?10/06 atr0621 the antenna supervisor software will be conf igured as follows: 1. enable control signal 2. enable short circuit detection (power down antenna via anton if short is detected via nantshort) 3. enable open circuit detection via naadet the antenna supervisor function may not be disabled by gpsmode pin selection. if the antenna supervisor function is not used, please leave open anton, nantshort and naadet. table 3-13. pin usage of active antenna supervisor pin usage meaning p0/nantshort nantshort active antenna short circuit detection high = no antenna dc short circuit present low = antenna dc short circuit present p25/naadet0/ miso or p14/naadet1 naadet active antenna detection input high = no active antenna present low = active antenna is present p15/anton anton active antenna power on output high = power supply to active antenna is switched on low = power supply to active antenna is switched off table 3-14. antenna detection i/o settings gpsmode11 (reset = pu) gpsmode10 (reset = pu) gpsmode8 (reset = pu) location of naadet comment 0 0 0 p25/naadet0/miso 001 (1) p25/naadet0/miso 01 (1) 0 p14/naadet1 reserved for further use. do not use this setting. 01 (1) 1 (1) p14/naadet1 (default rom value) 1 (1) 0 0 p14/naadet1 reserved for further use. do not use this setting. 1 (1) 01 (1) p14/naadet1 reserved for further use. do not use this setting. 1 (1) 1 (1) 0 p25/naadet0/miso 1 (1) 1 (1) 1 (1) p25/naadet0/miso note: 1. leave open
16 4890c?gps?10/06 atr0621 3.4 external connections fo r a working gps system figure 3-2. example of an external connection atr0601 atr0621 sigh sigl sc purf puxto sighi siglo clk23 rf_on see table 3-15 see table 3-15 see table 3-15 see table 3-15 see table 3-15 see table 3-15 gnd nc nc nc nc nc nc nc (see power supply) +3v nc: not connected (see power supply) +3v nc usb_dm usb_dp p18 optional usart 2 optional usart 1 optional usb p31 p21 xt_out xt_in p22 p20 p8 nreset em_da0 - 15 p9 - 15 p16 - 17 ldo_in ldobat_in vdd18 ldo_out ldo_en nshdn gnd dbg_en tdo ntrst tdi tck tms p23 - 30 p19 p0 - 7 status led timepulse nsleep em_a1 - 19 vbat vbat18 gnd vdd_usb +3v (see power supply) +3v (see power supply) vddio 32.368 khz (see rtc)
17 4890c?gps?10/06 atr0621 table 3-15. recommended pin connection pin name recommended external circuit p0/nantshort internal pull-down resistor, leave open if antenna supervision functionality is unused. p1/gpsmode0 internal pull-down resistor, leave open, in order to disable the gpsmode pi n configuration feature. connect to vdd18 to enable the gpsmode pin configuration feature. refer to gpsmode definitions in section ?setting gpsmode0 to gpsmode12? on page 11 . can be left open if configured as output by user application. p2/boot_mode internal pull-down resistor, leave open. p3/ncs1 output in default rom firmware: leave open, only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user application and is not always driven from external sources. p4/ncs0 output in default rom firmware: leave open, only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user application and is not always driven from external sources. p5/nwe/nwr0 output in default rom firmware: leave open, only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user application and is not always driven from external sources. p6/noe/nrd output in default rom firmware: leave open, only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user application and is not always driven from external sources. p7/nub/nwr1 output in default rom firmware: leave open, only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user application and is not always driven from external sources. p8/statusled output in default rom firmware: leave open, only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user application and is not always driven from external sources. p9/extint0 internal pull-up resistor, leave open if unused. p10/em_a0/nlb output in default rom firmware: leave open, only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user application and is not always driven from external sources. p11/em_a21/ncs2 output in default rom firmware: leave open, only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user application and is not always driven from external sources. p12/gpsmode2/npcs2 internal pull-up resistor, can be left open if the gp smode feature is not used or configured as output by user application. refer to gpsmode definitions in section ?setting gpsmode0 to gpsmode12? on page 11 . p13/gpsmode3/extint1 internal pull-up resistor, can be left open if the gp smode feature is not used or configured as output by user application. refer to gpsmode definitions in section ?setting gpsmode0 to gpsmode12? on page 11 . p14/naadet1 internal pull-down resistor, leave op en if antenna supervision functionality is unused. p15/anton internal pull-down resistor, leave open if antenna supervision functionality is unused. p16/neeprom internal pull-up resistor, leave open if no serial eeprom is connected. otherwise connect to gnd. p17/gpsmode5/sck1 internal pull-down resistor, can be left open if the gpsmode feature is not used or configured as output by user application. refer to gpsmode definitions in section ?setting gpsmode0 to gpsmode12? on page 11 . p18/txd1 output in default rom firmware: leave open if serial interface is not used. p19/gpsmode6/siglo1 internal pull-up resistor, can be left open if the gp smode feature is not used or configured as output by user application. refer to gpsmode definitions in section ?setting gpsmode0 to gpsmode12? on page 11 . p20/timepulse/sck2 output in default rom firmware : leave open if timepulse feature is not used. p21/txd2 output in default rom firmware: leave open if serial interface not used. p22/rxd2 internal pull-up resistor, leave open if serial interface is not used. p23/gpsmode7/sck internal pull-up resistor, can be left open if the gp smode feature is not used or configured as output by user application. refer to gpsmode definitions in section ?setting gpsmode0 to gpsmode12? on page 11 .
18 4890c?gps?10/06 atr0621 p24/gpsmode8/mosi internal pull-up resistor, can be left open if the gp smode feature is not used or configured as output by user application. refer to gpsmode definitions in section ?setting gpsmode0 to gpsmode12? on page 11 . p25/naadet0/miso internal pull-down resistor, leave open if antenna supervision functionality is unused. can be left open if configured as output by user application. p26/gpsmode10/nss/ npcs0 internal pull-up resistor, can be left open if the gp smode feature is not used or configured as output by user application. refer to gpsmode definitions in section ?setting gpsmode0 to gpsmode12? on page 11 . p27/gpsmode11/npcs1 internal pull-up resistor, can be left open if the gp smode feature is not used or configured as output by user application. refer to gpsmode definitions in section ?setting gpsmode0 to gpsmode12? on page 11 . p28/em_a20/ncs3 output in default rom firmware: leave open, only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user application and is not always driven from external sources. p29/gpsmode12/npcs3 internal pull-up resistor, can be left open if the gp smode feature is not used or configured as output by user application. refer to gpsmode definitions in section ?setting gpsmode0 to gpsmode12? on page 11 . p30/agcout0 internal pull-down resistor, leave open. p31/rxd1 internal pull-up resistor, leave open if serial interface is not used. em_da0 ? em_da15 if no external memory is used, could be leave open (internal pull-down). table 3-15. recommended pin connection (continued) pin name recommended external circuit
19 4890c?gps?10/06 atr0621 3.4.1 connecting an optional flash memory the atr0621 offers the possibilit y to connect an external fl ash memory. the high perfor- mance arm7 ? 32-bit risc processor of the atr0621 can be used to run application specific code, that is stored in the flash memory. the 32-bit risc processor of the atr0621 accesses the external memory via the ebi (external bus interface). atmel recommends to use 1.8v flash memory, e.g. the atmel at49sv802a. the ldo_out pin of the atr0621 can supply the external flash memory. figure 3-3 shows an example of the external flash memory connection. figure 3-3. example of an external flash memory connection at49sv802a atr0621 i/o0-15 a0-18 ce_n we_n oe_n nc nc vss gnd gnd nc reset_n byte_n ready/busy_n em_da0-15 em_a1-19 p4/ncs0 p5/nwe (see power supply) +3v nc: not connected ldo_in ldobat_in vdd18 ldo_out ldo_en nshdn gnd gnd p6/noe nreset
20 4890c?gps?10/06 atr0621 3.4.2 connecting an optional serial eeprom the atr0621 offers the possibility to connect an external serial eeprom. the internal rom firmware supports to store the configuratio n of the atr0621 in serial eeprom. the pin p16/neeprom signals the firmware that a se rial eeprom is connected with the atr0621. the 32-bit risc processor of the atr0621 accesses the external memory with spi (serial peripheral interface). atmel re commends to use 32 kbit 1.8v serial eeprom, e. g. the atmel at25320ay1-1.8. figure 3-4 shows an example of the serial eeprom connection. figure 3-4. example of a serial eeprom connection note: the gpsmode pin configuration feature c an be disabled, because the configuration can be stored in the serial eeprom. vddio is the supply voltage for the pins: p23, p24, p25 and p29. at25320ay1-1.8 atr0621 sck si so cs_n nc gnd gnd hold_n wp_n p23/sck p25/miso/naadet0 p24/mosi p29/npcs3 p16/neeprom p1/gpsmode0 (see power supply) +3v nc: not connected ldo_in ldobat_in vddio vdd18 ldo_out ldo_en nshdn gnd
21 4890c?gps?10/06 atr0621 4. power supply the baseband ic is supplied with four distinct supply voltages: vdd18, the nominal 1.8v supply voltage for the core, the rf-i/o pins, the memory interface and the test pins and all gpio-pins not mentioned in next item. vddio, the variable supply voltage within 1.8v to 3.6v for following gpio-pins: p1, p2, p8, p12, p14, p16, p17, p18, p19, p20, p21, p23, p24, p25, p26, p27 and p29. in input mode, these pins are 5v input tolerant. vdd_usb, the power supply of the usb pins: usb_dm and usb_dp. vbat18 to supply the backup domain: rtc, backup sram and the pins nsleep, nshdn, ldo_en, vbat18, p9/extin0, p13/extint1, p22/rxd2 and p31/rxd1 and the 32khz oscillator. in input mode, the four gpio-pins are 5v input tolerant. figure 4-1 , figure 4-2 and figure 4-3 show examples of the wiring of atr0621 power supply. figure 4-1. external wiring example using inte rnal ldos and backup power supply atr0621 internal vddusb 0v or 3v to 3.6v 1.5v to 3.6v 1 f (x7r) ldoout ldoen ldoin ldo18 ldo_in 1 f (x7r) vddio 2.3v to 3.6v ldo_en nshdn vdd18 ldo_out usb sm and transceiver 1.8v to 3.3v variable io domain rtc backup memory core vbat18 vbat vdd ldobat_in ldobat ldobat_in vbat vbat18
22 4890c?gps?10/06 atr0621 the baseband ic contains a built in low dropout voltage regulator ldo18. this regulator can be used if the host system does not provide the core voltage vdd18 of 1.8v nominal. in such case, ldo18 will provide a 1.8v supply voltage from an y input voltage vdd betw een 2.3v and 3.6v. it will also allow supplying extern al components such as flash memory with 1.8v. the ldo_en input can be used to shut down vdd18 if the system is in standby mode. if the host system does however supply a 1.8v core voltage directly, this voltage has to be con- nected to the vdd18 supply pins of the baseband ic. ldo_en must be connected to gnd. ldo_in can be connected to gnd. ldo_out must not be connected. a second built in low dropout voltage regulator ldobat provides the supply voltage for the rtc and backup sram from any input voltage vbat be tween 1.5v and 3.6v. the backup battery is only discharged if vdd - supplied via pin ldobat_in - is shut down. only after vdd18 has been supplied to atr0621 the rtc section will be initialized properly. if only vbat is applied first, the current consumption of the rtc and backup sram is undetermined. figure 4-2. external wiring example using 1.8v from host system and backup power supply atr0621 internal vddusb 0v or 3v to 3.6v 1.5v to 3.6v 1 f (x7r) ldoout ldoen ldoin ldo18 ldo_in 1 f (x7r) vddio ldo_en vdd18 ldo_out usb sm and transceiver 1.8v to 3.3v variable io domain rtc backup memory core vbat18 vbat vdd ldobat_in ldobat ldobat_in vbat vbat18 2.3v to 3.6v 1.65v to 1.95v
23 4890c?gps?10/06 atr0621 the usb transceiver is disabl ed if vdd_usb < 2.0v. in this case the pins usb_dm and usb_dp are connected to gnd (internal pull-down resistors). the usb transceiver is enabled if vdd_usb within 3.0v and 3.6v. figure 4-3. external wiring example using internal ldos , usb supply voltage and backup power supply atr0621 internal usb-vsb 5v vddusb 1.5v to 3.6v 1 f (x7r) ldoout ldoen ldoin ldo18 ldo_in 1 f (x7r) vddio ldo_en nshdn vdd18 external ldo 3.3v ldo_out usb sm and transceiver 1.8v to 3.3v variable io domain rtc backup memory core vbat18 vbat vdd ldobat_in ldobat ldobat_in vbat vbat18
24 4890c?gps?10/06 atr0621 5. rtc oscillator figure 5-1. crystal connection xt_in xt_out rtc atr0621 internal 32 khz crystal oscillator 32.768 khz clock 32.768 khz 50 ppm c c c = 2 c load , c load can be derived from the crystal datasheet. maximum value for c is 25 pf. 6. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters pin symbol min. max. unit operating free air temperature range ?40 +85 c storage temperature ?60 +150 c dc supply voltage vdd18 ?0.3 +1.95 v dc supply voltage vddio ?0.3 +3.6 v dc supply voltage vdd_usb ?0.3 +3.6 v dc supply voltage ldo_in ?0.3 +3.6 v dc supply voltage ldobat_in ?0.3 +3.6 v dc supply voltage vbat ?0.3 +3.6 v dc input voltage em_da0 to em_da15, p0, p3 to p7, p10, p11, p15, p28, p30, si ghi, siglo, clk23, xt_in, tms, tck, tdi, ntrst, dbg_en, ldo_en, nreset ?0.3 +1.95 v dc input voltage usb_dm, usb_dp ?0.3 +3.6 v dc input voltage p1, p2, p8, p9, p12 to p14, p16 to p27, p29, p31 ?0.3 +5.0 v note: minimum/maximum limits are at +25c ambi ent temperature, unless otherwise specified 7. thermal resistance parameters symbol value unit junction ambient, according to jedec51-9 r thja 36.9 k/w
25 4890c?gps?10/06 atr0621 8. electrical characteristics - dc characteristics if no additional information is given in column test conditio ns, the values apply to a temperature range from ?40c to +85c. no. parameters test conditions pin symbol min. typ. max. unit 1.1 dc supply voltage core vdd18 vdd18 1.65 1.8 1.95 v 1.2 dc supply voltage vddio domain (1) vddio vddio 1.65 1.8/3.3 3.6 v 1.3 dc supply voltage usb (2) vdd_usb vddusb 3.0 3.3 3.6 v 1.4 dc supply voltage backup domain (3) vbat18 vbat18 1.65 1.8 1.95 v 1.5 dc output voltage vdd18 v o,18 0vdd18v 1.6 dc output voltage vddio v o,io 0 vddio v 1.7 low-level input voltage vdd18 domain vdd18 = 1.65v to 1.95v v il,18 ?0.3 0.3 vdd18 v 1.8 high-level input voltage vdd18 domain vdd18 = 1.65v to 1.95v v ih,18 0.7 vdd18 vdd18 + 0.3 v 1.9 schmitt trigger threshold rising vdd18 = 1.65v to 1.95v clk23 v th+,clk23 0.7 vdd18 v 1.10 schmitt trigger threshold falling vdd18 = 1.65v to 1.95v clk23 v th-,clk23 0.3 vdd18 v 1.11 schmitt trigger hysteresis vdd18 = 1.65v to 1.95v clk23 v hyst,clk23 0.3 0.55 v 1.12 schmitt trigger threshold rising vdd18 = 1.65v to 1.95v nreset v th+,nreset 0.8 1.3 v 1.13 schmitt trigger threshold falling vdd18 = 1.65v to 1.95v nreset v th-,nreset 0.46 0.77 v 1.14 low-level input voltage vddio domain vddio = 1.65v to 3.6v v il,io ?0.3 +0.41 v 1.15 high-level input voltage vddio domain vddio = 1.65v to 3.6v v ih,io 1.46 5.0 v 1.16 low-level input voltage vbat18 domain vbat18 = 1.65v to 1.95v p9, p13, p22, p31 v il,bat ?0.3 +0.41 v 1.17 high-level input voltage vbat18 domain vbat18 = 1.65v to 1.95v p9, p13, p22, p31 v ih,bat 1.46 5.0 v 1.18 low-level input voltage usb v dd_usb = 3.0v to 3.6v dp, dm v il,usb ?0.3 +0.8 v 1.19 high-level input voltage usb vdd_usb = 3.0v to 3.6v, 39 ? source resistance + 27 ? external series resistor dp, dm v ih,usb 2.0 4.6 v 1.20 low-level output voltage vdd18 domain i ol = 1.5 ma, vdd18 = 1.65v v ol,18 0.4 v 1.21 high-level output voltage vdd18 domain i oh = ?1.5 ma, vdd18 = 1.65v v oh,18 vdd18 ? 0.45 v 1.22 low-level output voltage vddio domain i ol = 1.5 ma, vddio = 3.0v v ol,io 0.4 v 1.23 high-level output voltage vddio domain i oh = ?1.5 ma, vddio = 3.0v v oh,io vddio ? 0.5 v notes: 1. vddio is the supply voltage for the following gpio-pins: p1, p2, p8, p12, p14, p16, p17, p1 8, p19, p20, p21, p23, p24, p25, p26, p27 and p29 2. values defined for operating the usb interface. otherwise vdd_usb may be connected to ground 3. supply voltage vbat18 for backup domain is generated internally by the ldobat
26 4890c?gps?10/06 atr0621 1.24 low-level output voltage vbat18 domain i ol = 1 ma p9, p13, p22, p31 v ol,bat 0.4 v 1.25 high-level output voltage vbat18 domain i oh = ?1 ma p9, p13, p22, p31 v oh,bat 1.2 v 1.26 low-level output voltage usb i ol = 2.2 ma, vdd_usb = 3.0v to 3.6v, 27 ? external series resistors dp, dm v ol,usb 0.3 v 1.27 high-level output voltage usb i oh = ?0.2 ma, vdd_usb = 3.0v to 3.6v, 27 ? external series resistors dp, dm v oh,usb 2.8 v 1.28 input-leakage current (standard inputs and i/os) vdd18 = 1.95v v il =0 v i leak ?1 1 a 1.29 input capacitance i cap 10 pf 1.30 input pull-up resistor nreset r pu 0.7 1.8 k ? 1.31 input pull-up resistor tck, tdi, tms r pu 718k ? 1.32 input pull-up resistor p9, p13, p22, p31 r pu 100 235 k ? 1.33 input pull-down resistor dbg_en, ntrst, r pd 718k ? 1.34 input pull-down resistor rf_on, p0, p15, p30, em_da[0:15] r pd 100 235 k ? 1.35 configurable input pull-up resistor vddio = 3.6v p1, p2, p8, p12, p14, p[16-21], p[23-27], p29 r cpu 50 160 k ? 1.36 configurable input pull-down resistor vddio = 3.6v p1, p2, p8, p12, p14, p[16-21], p[23-27], p29 r cpd 40 160 k ? 1.37 configurable input pull-up resistor (idle state) usb_dp r cpu 0.9 1.575 k ? 1.38 configurable input pull-up resistor (operation state) usb_dp r cpu 1.425 3.09 k ? 1.39 input pull-down resistor usb_dp usb_dm r pd 10 500 k ? 8. electrical characteristics - dc characteristics (continued) if no additional information is given in column test conditio ns, the values apply to a temperature range from ?40c to +85c. no. parameters test conditions pin symbol min. typ. max. unit notes: 1. vddio is the supply voltage for the following gpio-pins: p1, p2, p8, p12, p14, p16, p17, p1 8, p19, p20, p21, p23, p24, p25, p26, p27 and p29 2. values defined for operating the usb interface. otherwise vdd_usb may be connected to ground 3. supply voltage vbat18 for backup domain is generated internally by the ldobat
27 4890c?gps?10/06 atr0621 10. esd sensitivity the atr0621 is an esd sensitive device. observe precautions for handling 11. ldo18 the ldo18 is a built in low dropout voltage regulator which can be used if the host system does not provide the core voltage vdd18. for well-defined start up of ldo18, ldo_in needs to be connected to ldobat_in. 9. power consumption mode conditions typ. unit sleep at 1.8v, no clk23 0.065 (1) ma shutdown rtc, backup sram and ldobat 0.007 (1) ma normal satellite acquisition 25 ma normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 ma 14 ma all channels disabled 11 ma note: 1. specified value only table 10-1. esd sensitivity test model max. with osc pins max. without osc pins unit human body model (hbm) 750 1000 v machine model (mm) 150 200 v charged device model (cdm) 250 500 v table 11-1. electrical characteristics of ldo18 parameter conditions min. typ. max. unit supply voltage ldo_in 2.3 3.6 v output voltage (ldo_out) 1.65 1.8 1.95 v output current (ldo_out) 80 ma current consumption after startup, no load, at room temperature 80 a current consumption standby mode (ldo_en = 0), at room temperature 15 a
28 4890c?gps?10/06 atr0621 12. ldobat and backup domain the ldobat is a built in low dropout voltage regulator which provides the supply voltage vbat18 for the rtc, backup sram, p9, p13, p22, p31, nsleep and nshdn. the ldobat voltage regulator switches in battery mode if ldobat_in falls below 1.5v. table 12-1. electrical characteristics of ldobat parameter conditions min. typ. max. unit supply voltage ldobat_in 2.3 3.6 v supply voltage vbat 1.5 3.6 v output voltage (vbat18) if switch connects to ldobat_in 1.65 1.8 1.95 v output current (vbat18) no external load allowed 1.5 ma current consumption ldobat_in (1) after startup (sleep/backup mode), at room temperature 15 a current consumption vbat (1) after startup (backup mode and ldobat_in = 0v), at room temperature 10 a current consumption after startup (normal mode), at room temperature 1.5 ma note: 1. if no current is caused by outputs (pad ou tput current as well as current across internal pull-up resistors)
29 4890c?gps?10/06 atr0621 14. package lfbga100 moisture sensitivity level (msl) = 3 13. ordering information extended type number package mpq remarks atr0621-7fqy lfbga100 2000 9 mm 9 mm, 0.80 mm pitch, rom4, pb-free, rohs-compliant atr0621n-7fqy lfbga100 2000 9 mm 9 mm, 0.80 mm pitch, rom5, pb-free, rohs-compliant atr0621p-7fqy lfbga100 2000 9 mm 9 mm, 0.80 mm pitch, rom5, pb-free, rohs-compliant ATR0621P1-7FQY lfbga100 2000 9mm 9 mm, 0.80 mm pitch, rom5, pb-free, rohs-compliant, automotive type atr0622-ek1 - 1 evaluation kit/road test kit atr0622-dk1 - 1 development kit including example design information specifications according to din technical drawings package: r-lfbga 100_g dimensions in mm ? 0.08 m a b c 9 0.05 9 0.05 7.2 0.8 a c c 0.2 c c 0.12 0.15 (4x) b seating plane 7.2 1.4 max (0.36) 0.53 ref. 0.27 ... 0.37 bottom view top view a1 corner a1 corner 1 a b c d e f g h j k a e d c b 2345 678910 1098 76 543 21 issue: 2; 27.10.05 drawing-no.: 6.580-5003.01-4 0.8 ? 0.15 m ? 0.38 ... 0.48 (100x) f k j h g
30 4890c?gps?10/06 atr0621 15. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4890c-gps-10/06 ? section 7 ?thermal resistance? on page 24 added ? section 13 ?ordering information? on page 29 changed 4890b-gps-06/06 ? table 3-1 ?atr0621 pinout? on pages 5-8 changed ? section 3.3 ?setting gpsm ode12? on page 11 changed ? table 3-4 ?enable configuration with gpsmode pins? on page 11 changed ? section 3.3.2 ?sens itivity settings? on page 12 changed ? table 3-5 ?gps sensitivity settings? on page 12 changed ? table 3-6 ?serial i/o configuration? on page 12 changed ? table 3-12 ?usb power modes? on page 14 changed ? table 3-14 ?antenna detection i/o settings? on page 15 changed ? figure 3.2 ?example of an external connection? on page 16 changed ? table 3-15 ?recommended pin connection? on pages 17-18 changed ? section 7 ?electrical characteristics - dc characteristics? on pages 25-26 changed ? section 10 ?ldo18? on page 27 changed
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